Almost everything a CPU can do can be reduced to some sort of logic equation. In math and theoretical computer science the most common logic operations are AND, OR and NOT. From an electrical point of view NOR and NAND gates are far more popular.
In theory every logic operation can be performed using only NAND gates. In practice it is more useful to use other gates as well. This post will describe how the different gates can be implemented using transistors and why, for my purposes, NAND and NOR are preferable over AND and OR.
I want to try building the CPU using only simple BC817 NPN transistors and resistors of a few discrete values. Limiting myself to only one transistor type and maybe 5 resistor values isn’t just an interesting challenge. It should also make the build process easier.
The BC817 itself is a fairly common and cheap general purpose transistor. In high volumes it can be bought for 1.5-2 cents per transistor. As a very rough estimation I expect to use some 1000 – 5000 transistors for the CPU itself, and anywhere between 1 000 and 500 000 transistors for the main memory (but I seriously doubt that I will fully equip the memory).
The basic logic gates are all fairly simple and well documented. This page gives a great overview of the different circuits. The general idea for all of these is to have the output pulled high or low when the transistor inputs are off. When activated the transistors will pull the output in the other direction.
The different gates simulated in LTSpice
After checking the gate circuits in LTSpice, we can see that the output of the non-negated gates is always ~ 0.7V lower than the output of the negated gates. In general the emitter of a silicon based NPN transistor will always be about 0.7V lower than its basis.
This can become a problem, if I want to chain multiple gates after each other. For a 5V input, the output of the gate will only be 4.3V. After two gates I only get 3.6V and soon the voltage will be too low to switch on the transistor.
If I want to stick to only NPN transistors, the simplest solution will be to build an AND gate as an inverted NAND gate.
New and improved gates, now with extra signal level!
Since the new versions of the AND and OR gate use an additional transistor and two additional resistors over the NAND and NOR versions, I will try to stick to the negated versions. If the in- and output conditions are well defined, I might also be able to use the simpler versions of the AND and OR gates.
Breakout boards for easier prototyping
To get a “feel” for these gates, I designed a generic breakout board for these gates.
The top is intentionally left blank
Each board can used as any gate, the function is selected through solder jumpers on the bottom. The pull-down resistors R11 and R12 are optional. If only NAND and NOR are needed, R13, R14 and T6 can be left unpopulated as well.
lots of jumpers
These basic boards allow me to play around with various combinations of logic gates, and see if the expected behaviour from the simulation matches the actual results. While I don’t expect any serious problems, I’d rather find out about them now, than later when a simple circuit might consist of 10s – 100s of transistors.
A 1-bit full adder built from basic logic gates
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